Junior digital IC verification Engineer

The required activities cover the area of verification of digital circuits, depending on the project needs, e.g.: understanding functional specifications (contributions if necessary), contribution to verification plan definition, working (definition, implementation, adaption, analysis) on reference models, verification components, verification environments and/or RTL components, verification and debug at different levels (block, system, gatelevel) using different methodologies, running regressions, run/create scripts for automation.

Your Qualifications – Solid and Appropriate
Interpersonal skills needed:

Nice to have

• Knowledge of scripting languages (Perl, Tcl/Tk, Python, sh, awk, etc.)
• Experience in verification methodologies (VMM/OVM/UVM/eRM, FormalVerification) and verification languages (e/SystemVerilog, PSL)
• Knowledge of modeling digital systems (Matlab/Simulink, SystemC)

• team player
• self-organized
• aim for a high quality standard
• willing to learn new things
• desire for self-improvements and innovations in the area of interest
• comfortable with processes within a large organization

Language skills

• English – mandatory
• German – is a plus
• eRM/VMM/OVM/UVM and languages VHDL/Verilog/ SystemVerilog/e (experience in Formal Verification is a plus)
• Good understanding of OOP (algorithms modeling using C/C++/SystemC/Matlab is a plus)
• Proficiency in Linux environments and scripting languages (Perl/Python/Tcl/sh)
• Strong knowledge of computer architectures,  interfaces, protocols (experience in implementation/verification of multi-core SoCs is a plus)
• Team player, aim for a high quality standard, like challenges, open to learn new things, desire for self-improvement and innovations
• Proficiency in English (German language is a plus)
• Miscellaneous- occasional or low to medium travelling is required, depending on the project needs