RF IC Verification Engineer Contract Job, Sweden
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Employer: | Inter-Consulting Europe (UK) Ltd |
Domain: |
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Job type: | full-time |
Job level: | 1 - 5 years of experience |
Location: |
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Updated at: | 10.07.2018 |
Remote work: | On-site |
Inter-Consulting Group relies on the synergy between quality consultants and customers to form long-term partnerships. It is the success of building these relationships with key customers, coupled with access to our extensive database of skilled consultants that has seen us grow from billings of £100k in 2006, IC has a steady repeat tunover of £5M per annum, keeping its key consultants in contract, partnered with existing long term and new customers. The areas covered are Nordics, USA, Canada, Latin America and Australia.
Inter-Consulting has a track record of over 15 years of consulting in niche markets. Our core e-business model has zero overheads, delivering our service online with access to a secure database matched to each client's requirements. This enables your managers to review a pre-matched pool of consultants via our www server to accelerate the placement process.
Required competence:
-Master degree or similar.
-Experienced in using the System Verilog tools and UVM methodology.
-Excellent programming skills (SV).
-Experience of SW design for an embedded environment.
-Knowledge of hardware design (VHDL/Verilog).
-Good knowledge of verification methodology in general.
-Experience in HW verification using e.g. OVM/UVM.
-Experience in system level verification.
-Experience in Formal Verification.
-Experienced in WCDMA, GSM and/or LTE systems.
-Good programming skills (C).
The job involves block verification within company´s digital ASIC and FPGA projects. The goal of the block verification is to verify that the functional requirements of product blocks are fulfilled before tape-out of the ASIC or release of the FPGA.
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used. A successful candidate is an experienced verification engineer with 5 or more years of IP module verification experience in System Verilog with the UVM methodology. Good understanding and knowledge about HW designs are also key factors. To have Specman, e knowledge and experience is a bonus. Good communication skills and interpersonal cooperation is required
Start date: ASAP (depends on the availability).
End Date: 6+months contract, ongoing.
Location: Lund, Stockholm.
If you are interested in this position, please apply with an up to date CV as soon as possible, along with your availability on ICEURO website
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