Staff Layout Engineer

Angajator: MICROCHIP TECHNOLOGY
Domeniu:
  • IT Hardware
  • IT Software
  • Tip job: full-time
    Nivel job: > 5 ani experienta
    Orase:
  • BUCURESTI
  • Actualizat la: 14.09.2017
    Scurta descriere a companiei

    Microchip Technology Inc. is a leading provider of microcontroller and analog semiconductors, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide. The Company offers outstanding technical support along with dependable delivery and quality. For more information, visit the Microchip website at www.microchip.com.

    Cerinte

    Job Requirements

    Degree in Electronics, Automatics or Electrical Engineering.
    Should have years experience in layout of CMOS logic, analog circuits, and chip-level products.

    Highly thorough and proficient at physical drawing with regard to execution of task, analog technique, area impact of decisions, power-bussing, latch-up, and circuit function

    Strong understanding and hands on experience using verification tools (Calibre and Hercules) for LVS & DRC

    Interact with design engineers both local and overseas to understand expectations and requirements of a project.

    Should have good knowledge of English and good communication skills.
    Microprocessor / microcontroller / memory layout experience or knowledge is a plus.

    Nice To Have

    Knowledge of Shell and scripting languages (skill, perl, tcl) and specific DRC/LVS verifications decks is a plus.

    Responsabilitati

    Job description:

    Design team member who is an active participate in layout design of modules and 8-bit mixed signal microcontrollers products.
    - Perform layout of CMOS modules and compact 8-bit products using Cadence tools.

    - Performs top level floorplanning, effort estimation, area optimization, project planning, and verification of analog, mixed-signal IC circuits.
    - Perform verification of layout adherence to design rules as well as Layout-vs-Schematic checks, ERC checks as well as parasitic extractions using specific tools from various vendors (Cadence, Synopsys, Mentor Graphics).

    - Performs quality checks at block level as well as chip level according to specific ISO/TS rules implemented in Microchip.

    - The candidate will be involved with the layout of flash and EEPROM memory macros and sub circuits too

    - Occasional travel to the US for short periods.