Backend Digital Design Intern
Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.Cerinte
- 4th year student in Electronics and Telecommunication, Automatics or Electrical Faculty
- Basic knowledge of digital design and integrated circuits fundamentals.
- Synopsis/Mentor/Cadence tools experience is a plus.
- Good knowledge of English and good communications skills
- Willingness to learn and keep up to date with latest flow definitions and design methodologies.
- Ability to interface with required functions and people in a multi-site, multi-national environment.
What do physical design engineers do?
- Physical design engineers are anonymous to city planners. They plan the Integrated Circuit layout.
- Physical Design Engineers do the layout assembling & connectivity of digital logic gates as per the design input file (netlist) of an IC (Integrated Chip) say a microcontroller, by meeting the design spec like frequency, area & power. They go on to optimize the circuit up and beyond, trying to increase its performance, until the design breaks. The varied technologies- from the outdated 180nm to the currently trending 7nm are the bread and butter of a physical design engineer. These refer to the channel length of the transistors. Other responsibilities include the synthesis of clock trees for easy routing, reducing delays and clearing the glitches.
- The development of the IC starts with planning, placement, and routing (PnR) through the multiple metal layers. The constrained development environment allows the testing of different corner cases. The synthesizable hardware description code is known as the netlist which the physical design engineer takes as ignition. After PnR, the resistances and capacitances of the design are calculated using RC extraction. This allows for a calculation of the bandwidth, quality factor, corner points.
- The optimized output is called the layout of the design. Signing off takes verification of the layout and the packaging of the design.
Responsiblities of the role:
- Responsible with semi-custom synthesis and STA for products developed in MCU16 division.
- In charge with execution of synthesis, scan insertion and STA steps, according to the Microchip design flow and using sign-off regulations as provided by the flow experts.
- Interfaces to top-level and module owners for taking over successive RTL releases, and performs top-level synthesis (Synopsys DC flow) ensuring timing closure and flow compliance.
- Interfaces to Physical Design Engineer (who is in charge with digital P&R + layout), delivering post-synthesis netlist and also taking over post-layout netlist delivery for STA.
- Performs STA using PrimeTime based on, and ensuring compliance to the latest sign-off regulations, computing ECO solutions as required (both for timing and functional fixes, as needed), as well as post-ECO STA updates.
- Has in-depth knowledge of timing theory and details, with an emphasis on analog/digital interfaces, hard-macro functionality and connected topics.