Backend Digital Design Intern

Angajator: MICROCHIP TECHNOLOGY
Domeniu:
  • Inginerie
  • Tip job: part-time
    Nivel job: Student/Absolvent
    Orase:
  • BUCURESTI
  • Actualizat la: 22.01.2022
    Scurta descriere a companiei

    Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

    Cerinte

    •4th year student in Electronics and Telecommunication, Automatics or Electrical Faculty
    • Basic knowledge of digital design and integrated circuits fundamentals.
    • Synopsis/Mentor/Cadence tools experience is a plus.
    • Good knowledge of English and good communications skills
    • Willingness to learn and keep up to date with latest flow definitions and design methodologies.
    • Ability to interface with required functions and people in a multi-site, multi-national environment.

    Responsabilitati

    • Responsible with semi-custom synthesis and STA for products developed in MCU16 division.
    • In charge with execution of synthesis, scan insertion and STA steps, according to the Microchip design flow and using sign-off regulations as provided by the flow experts.
    • Interfaces to top-level and module owners for taking over successive RTL releases, and performs top-level synthesis (Synopsys DC flow) ensuring timing closure and flow compliance.
    • Interfaces to Physical Design Engineer (who is in charge with digital P&R + layout), delivering post-synthesis netlist and also taking over post-layout netlist delivery for STA.
    • Performs STA using PrimeTime based on, and ensuring compliance to the latest sign-off regulations, computing ECO solutions as required (both for timing and functional fixes, as needed), as well as post-ECO STA updates.
    • Has in-depth knowledge of timing theory and details, with an emphasis on analog/digital interfaces, hard-macro functionality and connected topics.