Functional Verification Engineer
ALTEN Romania offers technical consulting services, with a team of over 500 engineering and IT specialized consultants in its offices in Bucharest, Timisoara, Cluj, Sibiu and Iasi.Requirements
• A Master’s degree or/and a Bachelor’s degree in Electrical/Electronic Engineering or equivalent.
• 3-4 years’ experience in verification environment (is a MUST!)
• Proven experience within a High Level Verification Language (System Verilog/Specman).
• Good understanding of Verilog/VHDL and the ability to debug digital circuits on RTL and gate level.
• Knowledge of Object Oriented Programming.
• Knowledge of a scripting language (e.g. TCL, bash, perl, Python).
• Good command of English Language.
• Review functional specifications and define the verification strategy (e.g. verification plan and verification environment architecture) based on the HW specification.
• Build the verification environment following the verification methodologies (i.e. UVM, eRM).
• Implement the verification model of the DUT and the verification components for driving, monitoring and checking different digital modules, at SOC level and mixed signal testing.
• Develop test scenarios and functional coverage based on the verification plan.
• Create and support innovative ideas in your field of knowledge collaboratively and have measurable impact on working results on a local basis and within organizational area.
• Contribute to success and give technical guidance in the project / team.
• Share knowledge within project / team and demonstrate active knowledge transfer and best practice sharing.