- Design team member who is an active participant in layout design of analog products;
- Perform layout of CMOS analog circuits using Cadence tools;
- Perform verification of layout adherence to design rules (DRC) and Layout-vs-Schematic checks;
- Complete tapeout procedures.
- 3rd / 4th year student or at Master in Electronics and Telecommunication or Electrical Faculty
- Should have experience in layout of CMOS analog circuits;
- Should have good knowledge of English and good communication skills.