Senior Verification Engineer

ALTEN Romania, part of the international ALTEN Group - with a unique position as Leader in IT & Engineering Consulting, provides support for its clients’ development strategies in the fields of innovation, R&D and IT systems since 1996. The company comprises 2 divisions specialized on its core capabilities: ENGINEERING and IT. These two divisions are: ALTEN TECHNO and ALTEN IT.

Technical Skills:
• Familiar with SV or Specman
• Very good knowledge with respect to UVM or eUVM
• Very good understanding of object-oriented programming principles
• Able to derive verification plans from specifications and requirement data bases
• Experienced in building up block or chip level environments including verification components, constraint random stimulus, assertion- as well as scoreboard-based checks and functional coverage models
• Familiar with typical simulator and debugging environments (e.g. Cadence Incisive)
• Able to run and analyze regressions using verification cockpits (e.g. Cadence Vmanager)
• Proficient user of data management tools (e.g. ClearCase or git)
• Able to perform Formal Verification using a typical tool (e.g. Onespin360)
• Basic understanding of RTL design and behavioral modelling with VHDL and Verilog
• Proficient user of Linux-based OSs and typical scripting languages (e.g. Python or Perl)
• Able to work with a typical bug tracking platform (e.g. Atlassian JIRA).

Soft Skills:
• Communication
- Able to abstract technical details
- Open to communicate with people on and off site
- Open communication style
- Good level of English.
• Team player
- Committed to the team and task
- Helping team members, sharing knowledge.
• Self motivated
- Embracing the task
- Highlight potential issues
- Regular reporting
- Clean and organized working style
- Following and improving processes.
• Able to follow corporate reporting standards.

• Create verification plans and test suites based on design micro-architecture and design specification
• Build effective verification environment (module level and system level)
• Analysis of functional/code coverage and performance
• Debug designs (VHDL, Verilog) and publish verification status
• Conduct netlist gate level simulation.