FPGA Verification Engineer Contract Job Sweden

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Employer: Inter-Consulting Europe (UK) Ltd
Domain:
  • IT Hardware
  • IT Software
  • Job type: project-based
    Job level: 1 - 5 years of experience
    Location:
  • BUCHAREST
  • Abroad
  • Timisoara
  • Updated at: 10.06.2019
    Short company description

    Inter-Consulting Group relies on the synergy between quality consultants and customers to form long-term partnerships. It is the success of building these relationships with key customers, coupled with access to our extensive database of skilled consultants that has seen us grow from billings of £100k in 2006, IC has a steady repeat tunover of £5M per annum, keeping its key consultants in contract, partnered with existing long term and new customers. The areas covered are Nordics, USA, Canada, Latin America and Australia.

    Inter-Consulting has a track record of over 15 years of consulting in niche markets. Our core e-business model has zero overheads, delivering our service online with access to a secure database matched to each client's requirements. This enables your managers to review a pre-matched pool of consultants via our www server to accelerate the placement process.

    Requirements

    We are looking for an FPGA verification engineer to enter into an existing cross-functional development team for embedded development in Telecommunications.
    The main task is to lead the verification of a porting and upscaling project of existing VHDL and Verilog code from one FPGA family to another and addition of functionality.
    The project includes the latest and largest cutting-edge FPGA from Intel/Altera and is at the very forefront of Telecommunications development that will result in technology for the next generation of mobile communication.
    The way of working is agile and strong team working capabilities are essential to be a successful candidate.

    Responsibilities

    Experience with top level verification with medium to large FPGA designs
    Experience in SystemVerilog/UVM
    Block- and/or Top level verification
    Random and directed tests on block level and top level
    VHDL/Verilog programming experience
    Experience with Xilinx and/or Altera platform and tools (Quartus or ISE etc.)

    Other info


    Start Date: ASAP
    End Date: 6+ months